The invention is directed to a read-only memory for a gate array arrangement upon employment of basic cells that contain at least one n-channel and p-channel transistor.
Gate array arrangements are known (for example, Hitachi review, Vol. 33, 1984, No. 5, Pages 261-26). In such gate array arrangements, cell regions or cells are provided in a defined arrangement on a chip, basic cells being realized thereon. The basic cells are composed of n-channel and p-channel transistors that are arranged in the cell regions. The basic cell can be specified for the realization of a basic function by connecting the n-channel transistors and p-channel transistors per basic cell and, for example, it can be lent a logical function or a memory function.
The individual basic cells in the gate array arrangement must be connected to one another for setting functions. This then occurs via wiring channels that are conducted past between the lines of basic cells or over lines of basic cells.
The realization of memories having differing capacity was previously achieved in various ways. Bistable circuits were employed for storing structures having low capacity. These are composed of a plurality of gates and therefore require comparatively many basic cells of a gate array for storing an information unit. High-capacity memories were realized in that a memory having block-defined capacity designed as a general cell was integrated in the region of the chip. This led thereto that the capacity of a memory can be selected only in steps of the memory capacity of this general cell (also referred to as macrocell). Finally, the space requirement for such memories was relatively high since wiring channels had to be arranged between the lines of basic cells.
Read-only memories upon employment of MOS transistors are known (for example, H. Weiss, K. Horninger, Integrierte MOS-Schaltungen, Halbelektronik 14, Springer-Verlag 1982, Pages 232,233). For storing an information unit of the one type, for example "1", a MOS transistor has its controlled path arranged between a supply potential and a bit line and has its gate electrode connected to a word line. For storing an information unit of the other type, for example, "0", no MOS transistor is arranged at the intersections between bit line and word line. It does not derive from the reference, however, how a read-only memory of this principle can be realized in gate array arrangements upon employment of given basic cells.